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raw | patch | inline | side by side (parent: 1482410)
i.MX6: define CACHELINE_SIZE
authorEric Nelson <[email protected]>
Sun, 4 Mar 2012 11:47:37 +0000 (11:47 +0000)
committerAlbert ARIBAUD <[email protected]>
Mon, 16 Apr 2012 12:53:58 +0000 (14:53 +0200)
Signed-off-by: Eric Nelson <[email protected]>
Acked-by: Marek Vasut <[email protected]>
arch/arm/include/asm/arch-mx6/imx-regs.h patch | blob | history

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index cad957a3b77283f6ab2e5d4988572b35eb576e07..1033d056fc44617a999f38a0a45fd3c4cd656bc5 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -19,6 +19,8 @@
 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
 #define __ASM_ARCH_MX6_IMX_REGS_H__
 
+#define CONFIG_SYS_CACHELINE_SIZE      32
+
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
 #define CAAM_ARB_BASE_ADDR              0x00100000
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